TM 1-2840-252-23-3
b. To View Current Faults and Faults From Last Engine Run. Faults displayed in shutoff cannot be cleared until
the engine is run above 48 percent N1.
(1) Turn on power to DECU.
(2) Set engine condition lever (ECL) to stop position.
(3) The display will indicate current fault codes and fault codes from the last engine run in sequence. After
all applicable fault codes have been displayed, the sequence will repeat. If there are no applicable
fault codes, an "88" will be displayed. Record all codes displayed.
NOTE
If an ECL fault occurs, the DECU holds the second to last good ECL value until DECU power is removed.
If the ECL fault is still present when DECU power is reapplied, the ECL value defaults to GROUND.
Therefore, if the second to last good ECL value is FLIGHT, the hex display will not display any faults until
DECU power is cycled. If the second to last good ECL value is GROUND, the hex display will display both
current faults and faults from the last engine run until DECU power is cycled. In either case , when DECU
power is reapplied, the ECL value will default to GROUND, and only current faults. can be displayed until
the ECL fault has been cleared.
G-8 POWER SUPPLY INTERRUPT
a. The DECU is designed to operate normally with three separate power buses. The primary control lane is
powered by either the engine HMA alternator ( 8V ALT) at engine speeds greater than idle, or the 28V
2
airframe DC bus (28V AF) whichever is higher. The reversionary control lane is powered by either 28V AF or
the 28V emergency bus (28V EM),whichever is higher. During pilot generator switching actions, which
normally take place at flight idle conditions before and then subsequent to a flight, simultaneous aircraft bus
interrupts on the 28V AF and 28V EM can occur, causing the reversion control lane to be depowered. The
primary control lane continues operating normally since it is receiving its power from 28V ALT.
b. The primary lane monitors specific reversionary lane signals. When both power supplies to reversionary are
interrupted, these signals are temporarily seen as out of range by the primary lane. If the interrupts are of
sufficient duration (>50ms), the primary lane will latch the faults. The faults remain latched in primary until
primary lane power is removed, even if a reversionary reset has cleared the reversionary lane of all faults.
The end result is one or more nuisance faults that are due to the power interruption, not to an actual FADEC
problem. The possible faults are listed below. The actual combination of faults will depend on both the
operating conditions at the time of the interrupt and the duration of the interrupt. FADEC faults caused by
power interrupts are expected to be an occasional random occurrence, not a regular occurrence.
G-7
